JOB POSTING INFORMATION
Position Type:	Professional Experience Year Co-op (PEY Co-op: 12-16 months)
Job Title:	FY24 Intern - QCT Canada Display IP Engineering Internship
Job Location:	Markham, ON
Job Location Type:	On-Site
Number of Positions:	1
Salary:	Salary Not Available, 0.0 hours per week
Start Date:	05/01/2024
End Date:	08/29/2025
Job Function:	Engineering
Job Description:	Qualcomm Overview: Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age - and this is where you come in. General Summary: Internship Job Positions with Display Hardware Team  Display ASIC Design Implementation Intern  Display ASIC Design Verification Intern  Display ASIC Silicon Validation and Emulation Intern  Display ASIC System Intern  Job Description  Before there were smartphones or smart cities, before autonomous cars or 360° virtual reality videos, there was our technology. Headquartered in San Diego, for over 30 years Qualcomm inventions have inspired others to make the impossible, possible. From 5G to artificial intelligence, IoT to automotive and extended reality applications, Qualcomm is inventing the technologies of an intelligently connected future, spearheading research efforts for the next global wireless standard, and collaborating with industry leaders in the wireless value chain to make this future a commercial reality.      We are looking for bright, energetic, motivated students to join Qualcomm’s Canada internship class!      In a world where power and capabilities keep increasing to compete with other leading companies in the industry, be a member of the team that develops the high-performance Snapdragon Display Processor. Learn details of high-performance processing engines covering all aspects including core functionality, performance/power validation and customer use-cases and gain exposure to industry leading edge HW Design processes and methodology.      When applying, you can specify which project(s) you would like to be considered for.  By applying here, you are expressing interest in one of our many Qualcomm Display IP Engineering internships. It is important to note that this is not a job posting for a specific role. We will review resumes on an ongoing basis, and a recruiter may reach out to you.       Successful candidates will have experience in one of the following project areas:      For Display ASIC Design Implementation Intern, Key Responsibilities are:   Contribute to RTL (Verilog) design for next generation Snapdragon Display Processors.   Integration of external IP’s and design of interfacing logic into the Display Subsystem.   Work with the latest sub-micron technology nodes.   Use industry standard CAD tools for RTL Linting, power analysis, and CDC Analysis. Develop a strong foundation in good digital design practices.    Participate in experiments to optimize the Display design across power, area, and performance targets.    Using scripting languages (perl, python) to enhance existing methodologies, automate manual processes, and devise new tools for design development.        For Display ASIC Design Verification Intern, Key Responsibilities are:   Own IP core level feature verification during the design and development phase of next generation ASICs through C/RTL and Gate Level simulations.   Learn and get in-depth experiences with Display technologies and advance verification methodology and tools   Participate in test plan development and execution and verification closure in conjunction with the ASIC teams.   Contribute to creating/maintaining a test bench, assertions, and functional coverage models.   Contribute to implementing flows to automate development processes.   Participate in debug activities throughout the development cycle.       For Display ASIC Silicon Validation and Emulation Intern, Key Responsibilities are:   Contribute to IP verification during the pre/post silicon phase of next generation ASICs through emulation (FPGA), and/or silicon validation using high speed lab equipment (oscilloscopes, protocol analyzers, etc)   Participate in test plan development and execution and verification closure in conjunction with the ASIC teams   Contribute to implementing flows to automate development processes   Participate in debug activities through the development cycle (pre and post-silicon)   Using C/C++/Perl.Python to develop new tests or enhance existing test suites     For Display ASIC System Intern, Key Responsibilities are:   Contribute to system level performance and functional analysis of next-generation Snapdragon Display processors.  Working with SW/CE/AU teams to help resolve time-critical issues.   Exposure to interact and work with many cross-functional teams (design, DV, SVE, SW, CE, Marketing).  Use scripting Perl/Python) and data analysis (Excel) to help root-cause issues.   Create new tools for performance and functional analysis.
Job Requirements:	Minimum Qualifications:   In study towards a bachelors in one of the following: Electrical Engineering, Computer Engineering, Computer Science or related field   Must be available from May 2024 - August 2025   Knowledge of a programming language and scripting. Preferably some experience with lab equipment - scopes, etc. School projects with FPGAs a nice to have.   RTL / Verilog / System Verilog, Digital Design, Linux   Good communication skills, Teamwork   Object Oriented Programming (OOP), VHDL, C, C++, Digital Circuits   Real-Time Operating Systems   Computer Hardware (Caches, Busses, Memories, Clocking)   Preferred Qualifications:   Synthesis, perl, python tcl   MIPI DSI, HDMI, DisplayPort, AXI, AHB, Perl, Python, TCL, TCSH, GNU Make   Digital Signal Processing, FPGA fundamentals   Pixel and video processing ​  *not all preferred for every project
Preferred Disciplines:	Computer Engineering Computer Science Electrical Engineering Engineering Science (Electrical and Computer)
All Co-op programs:	No
Targeted Co-op Programs:	Targeted Programs Professional Experience Year Co-op (12 - 16 months)

APPLICATION INFORMATION
Application Deadline:	Oct 27, 2023 11:59 PM
Application Receipt Procedure:	Employer Website
If by Website, go to:	https://careers.qualcomm.com/careers/job/446695217861
Additional Application Information:	Note to PEY Co-op applicants: In addition to your application by email/website, please ensure that you select the “I intend to apply for this position” tab on the portal.  This will give us a record of your submitted application in the event that you will be invited for interviews. Apply via employer website: https://careers.qualcomm.com/careers/job/446695217861
U of T Job Coordinator:	Kaisa Moran

ORGANIZATION INFORMATION
Organization:	Qualcomm Canada Inc.
Division:	Markham Toronto Design

ADDITIONAL INFORMATION
Length of Workterm:	FIXED PEY Co-op: 16 months